The present invention relates to a computer comprising a central processor, a memory for storing information connected to the processor and to at least one controller for a peripheral unit, and a logic unit for control of the memory. Computers are known wherein one or more peripheral unit controllers can access the information contained in the memory singly and directly without engaging the central processor; such access is commonly called DMA (direct memory access). According to the DMA operation, the concerned peripheral unit interrupts the addressing operations of the central processor, replacing the processor in accessing the memory. This procedure entails a delay in the execution of the program of the central processor inasmuch as simultaneous requests for access by the peripheral unit controller and the central processor are resolved sequentially.